1. Field of the Invention
The present invention relates to voltage controlled current sources and bias generation circuits using such a current source. The invention relates more particularly to a voltage controlled current source outputting a current according to a control voltage and a bias generation circuit outputting a bias voltage according to a control voltage.
2. Description of the Background Art
Bias voltage which changes depending upon input voltage V.sub.I is necessary, for example, in a voltage controlled oscillator (VCO). FIG. 7 is a block diagram showing the structure of a general voltage controlled oscillator. Referring to FIG. 7, the voltage controlled oscillator includes a ring oscillator 61 having three stages of inverters 62 connected to a power supply node 70 and a ground node 71 through current sources 63 and 64, and a bias generation circuit 51 for generating bias voltages V.sub.BP and V.sub.BN to control current sources 63 and 64, and the oscillation frequency f of the oscillator changes depending upon input voltage V.sub.I. Power supply voltage V.sub.DD is applied to power supply node 70, and ground node 71 is grounded. A transistor forming a current mirror connection with a transistor in bias generation circuit 51 is generally used for current source 63, 64.
FIG. 8 is a circuit diagram showing the structure of bias generation circuit 51. Referring to FIG. 8, bias generation circuit 51 includes a P channel MOS transistor 55 connected in series between power supply node 70 and ground node 71, a first output node N51, an N channel MOS transistor 52, a resistor 53, a P channel MOS transistor 56 also connected in series between power supply node 70 and ground node 71, a second output node N52, and an N channel MOS transistor 57. The gates of P channel MOS transistors 55 and 56 are connected together to first output node N51, and the gate of N channel MOS transistor 57 is connected to second output node 52. P channel MOS transistor 55 and 56 constitute a current mirror circuit 54. The gate of N channel MOS transistor 52 is provided with input voltage V.sub.I, and bias voltages V.sub.BP and V.sub.BN are output from first and second output nodes N51 and N52, respectively.
Assuming that P channel MOS transistors 55 and 56 are the same in size, and that bias current driven by N channel MOS transistor 52 is I.sub.B, current through the path in the right, in other words current through P channel MOS transistor 56 and N channel MOS transistor 57 is I.sub.B. A transistor constituting a current mirror connection with P channel MOS transistor 55 or N channel MOS transistor 57, in other words a transistor which uses bias voltage V.sub.BP or V.sub.BN as a gate voltage forms a current source r times as large as bias current I.sub.B, where the ratio of the sizes of the transistors is r.
FIG. 9 is a graph showing the relation between input voltage V.sub.I and bias current I.sub.B. As can be seen from FIG. 9, in the conventional bias generation circuit 51, in the region in which input voltage V.sub.I is larger than the threshold voltage V.sub.I of N channel MOS transistor 52, bias current I.sub.B increases linearly with increase in input voltage V.sub.I, while in the region in which input voltage V.sub.I is smaller than the threshold voltage V.sub.TN Of N channel MOS transistor 52, bias current I.sub.B is cut off (null).